1. Field of the Invention
The present invention relates to pad structures of space transformers and methods thereof.
2. Description of the Related Art
With the advance of electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other integrated devices or circuits. Due to high-integration of chips, dimensions of semiconductor devices have been reduced, and various package structures and methods have been proposed. Test apparatus must also be designed, in order to test these package structures.
FIG. 1 is a schematic cross-sectional view of a probe card attached to a test apparatus.
Referring to FIG. 1, the test apparatus comprises the printed circuit board (PCB) 100, the iron frame 110, the space transformer 120, the upper die 130, the cobra head 140 and the lower die 150. The space transformer 120 is attached to the PCB 100 through a ball-grid array (BGA) or a pin-grid array (PGA). The surface 125 of the space transformer 120 is attached to the guide plate 130. The pins (not shown) of the guide plate 130 contact pad structures (not shown) at the surface 125 of the space transformer 120. The cobra head 140 and the lower die 150 are then sequentially attached to the guide plate 130. Because tests of chips require various space transformers corresponding thereto, the guide plate 130 and the space transformer 120 are disassembled from the test apparatus to change a desired space transformer.
FIG. 2 is a cross-sectional view of a prior art space transformer.
The space transformer 120 comprises a plurality of pad structures 120a therein. The pad structures 120a are made of copper. While being assembled with the space transformer 120, the pins 105 of the guide plate 130 move upward to contact with the pad structures 120a of the space transformer 120. Due to the softness of copper, the pins 105 usually penetrate into the pad structures 120a of the space transformer 120. After making contact several times, the pins 105 may penetrate through the pad structures 120a of the space transformer 120 and touch the matrix of the space transformer 120. This phenomenon results in contamination at the tips of the pins 105 or creates particles. In some worst-case scenarios, a misalignment exists between the guide plate 130 and the space transformer 120. The pins 105 of the guide plate 130 touches the corners 115 of the space transformer 120, which are not made of metallic materials. This phenomenon also causes contamination and particles during the assembly of the guide plate 130 and the space transformer 120.
U.S. Pat. No. 6,794,680 describes a semiconductor device. The semiconductor device has a pad, a first conductor and a second conductor, which are arranged at a surface of the pad. The first conductor has hardness that is greater than that of the second conductor and not less than that of a probe stylus. The first conductor is arranged at the surface of the pad such that the probe stylus hits or rubs against the first conductor at least one time while the probe stylus is in contact with and sliding on the surface of the pad.
U.S. Patent Application No. 2005/0242446 provides a manufacturing method for an integrated circuit package. In such a method, a contact pad is formed under a passivation layer on an integrated circuit. An opening is formed in the passivation layer exposing the contact pad. An “under bump metallurgy” is formed over the contact pad and the passivation layer. The method further includes forming a bump pad over the “under bump metallurgy” of a material having a first hardness and forming a bump on and over the bump pad. The bump has a top flat surface and of a material having a second hardness softer than the first hardness.
Improved pad structures of the space transformer and methods of forming pad structures are desired.